This invention relates generally to instruction set computing. In particular, the invention relates to a method of executing an instruction set, and an execution processor for executing the instruction set.
Reduced instruction set computing (RISC) processors typically have a fixed bit-width instruction size. Common sizes are 16-bits and 32-bits. 32-bits give flexibility in expressing instructions and operands but at the expense of typically larger code size than the 16-bit instruction sets.
Some instruction sets incorporate an instruction to select multiple registers. For example a “push” instruction is an instruction which identifies one or more registers the contents of which are to be pushed onto a data stack. Similarly, a “pop” instruction is an instruction which identifies one or more registers the contents of which are to be popped off a data stack. Known instructions of these types identify the registers to be selected using a bit map. Each bit in an operand of the instruction corresponds to a respective register. Those registers for which the respective bit is a 1 in the bit map are pushed/popped. This type of bit-map instruction is efficient because it identifies multiple registers in one instruction and hence allows multiple registers to be pushed in one clock cycle. However, this type of instruction cannot readily be implemented in reduced instruction sets which use short instructions. This is because there are not enough bits in the short instructions to specify both the operator indicating that the instruction relates to pushing/popping registers and the operands indicating which registers are to be pushed/popped.
It is also known to specify registers by means of a lookup table. In this arrangement, the entries of the lookup table are common register combinations. An instruction can identify one of these common register combinations by specifying the appropriate entry in the lookup table. This enables multiple registers to be identified using only the number of bits required to identify the lookup table entry. This method is therefore suitable for use with reduced instruction sets which do not have a large supply of available bits. However, this method is limited in that only the common register combinations in the lookup table can be specified by the instruction. For uncommon register combinations the problem remains that the short instructions of a reduced instruction set are too short to specify both the operator indicating that the instruction relates to pushing/popping registers and the operands indicating which registers are to be pushed/popped.
There is therefore a need for a method of executing a reduced instruction set in which multiple registers can be more efficiently specified.